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revision-01, 17th July '00
MITSUBISHI LSIs
M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs organized as 262,144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.25m CMOS technology . The M5M5V416B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416BUG is packaged in a CSP (chip scale package), with the outline of 7mm x 8.5mm, ball matrix of 6 x 8 (48pin) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards.
Those are summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply Small stand-by current: 0.3A(3V,ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.25m CMOS Package: 48pin 7mm x 8.5mm CSP
Version, Operating temperature Part name
Power Supply
Access time
max.
Activ e current ty pical * Ratings (max.) Icc1 25C 40C 25C 40C 70C 85C (3.0V, ty p.) Stand-by c urrent Icc(PD), Vcc=3.0V 50mA (10MHz) 7mA (1MHz)
I-v ersion
-40 ~ +85C
M5M5V416BUG -70HI
2.7 ~ 3.6V
70ns
0.3A
1A
1A
3A
15A 30A
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION
1 A B C D E F G H
BC1
(TOP VIEW)
2
OE
3
A0
4
A1
5
A2
6
S2
Pin
DQ9 BC2 A3 A4 S1 DQ1
Function Address input Data input / output Chip select input 1 Chip select input 2 Write control input Output enable input Lower By te (DQ1 ~ 8) Upper By te (DQ9 ~ 16) Power supply Ground supply
A0 ~ A17
DQ10 DQ11 A5 A6 DQ2 DQ3
DQ1 ~ DQ16
S1
GND DQ12 A17 A7 DQ4 VCC
S2 W OE BC1 BC2 Vcc GND
VCC
DQ13
GND
A16
DQ5
GND
DQ15
DQ14
A14
A15
DQ6
DQ7
DQ16
N.C.
A12
A13
W
DQ8
N.C.
A8
A9
A10
A11
N.C.
Outline: 48FJA NC: No Connection
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416BWG is organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply c urrent is reduced as low as 0.3A(25C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 S2 BC1 BC2 W OE HXX X XX XL XX LH LH L L L L L L L H H H H H H H X H L L L H H H L L L X H H H H L L L L L L X X L H H L H H L H H X X X L H X L H X L H Mode
Non selection Non selection Non selection
DQ1~8
DQ9~16 Icc High-Z High-Z Standby
High-Z High-Z Standby High-Z High-Z Standby Din High-Z Activ e Dout High-Z Activ e High-Z High-Z High-Z Din High-Z Dout High-Z High-Z Din Din Dout Dout High-Z High-Z Activ e Activ e Activ e Activ e Activ e Activ e Activ e
Write Read Write Read Write Read
BLOCK DIAGRAM
A0 A1 MEMORY ARRAY 262144 WORDS x 16 BITS A16 A17 S1 S2 BC1 BC2 W
CLOCK GENERATOR
DQ 1
DQ 8
-
DQ 9
DQ 16
Vcc
GND OE
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C I-v ersion Ratings Units
Vcc VI VO Pd Ta T stg
-0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 - 40 ~ +85 - 65 ~ +150 mW
C C
V
* -3.0V in case of AC (Pulse width < 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=2.7 ~ 3.6V, unless otherwise noted) Conditions Limits Min Ty p Max Vcc+0.3V Units
Parameter High-lev el input v oltage Low-lev el input v oltage
High-level output voltage 1 High-level output voltage 2
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2
Low-lev el output v oltage Input leakage current Output leakage current Activ e supply c urrent ( AC,MOS lev el ) Activ e supply c urrent ( AC,TTL lev el )
IOH= -0.5mA IOH= -0.05mA IOL=2mA VI =0 ~ Vcc
BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc BC1 and BC2< 0.2V, S1< 0.2V, S2 Vcc-0.2V = = > other inputs < 0.2V or = Vcc-0.2V = Output - open (duty 100%)
2.2 -0.3 * 2.4
Vcc-0.5V
0.6 V 0.4 1 1 70 15 70 15 40 20 5.0 2.0 2.0 2.0 0.5 mA A
A
f = 10MHz f = 1MHz f = 10MHz f = 1MHz +85C +70C +40C 0 ~ +25C - 20 ~ +25C - 40 ~ +25C
BC1 and BC2=VIL , S=V IL ,S2=V IH other pins =V IH or VIL Output - open (duty 100%) <1>
> S1 = Vcc - 0.2V,
-
50 7 50 7 1 0.3 0.3 0.3 -
mA
other inputs = 0 ~ Vcc <2>
Icc3
Stand by s upply current ( AC,MOS lev el )
S2 <3>
0.2V,
other inputs = 0 ~ Vcc
> BC1 and BC2 = Vcc - 0.2V > S1 < 0.2V, S2 = Vcc - 0.2V =
Other inputs=0~Vcc
Icc4
Stand by s upply current ( AC,TTL lev el )
BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25C
* -3.0V in case of AC (Pulse width < 30ns) =
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions
(Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Ty p Units
Min VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz
Max
CI CO
10 10
pF
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revision-01, 17th July '00
MITSUBISHI LSIs
M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply v oltage Input pulse
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7V~3.6V VIH=2.4V,VIL=0.4V Input rise time and f all time 5ns
Ref erence lev el
1TTL DQ CL
Including scope and jig capacitance
VOH=VOL=1.5V
Transition is measured 500mV f rom steady state voltage.(f or ten,t dis)
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address Units Min 70 70 70 70 70 70 35 25 25 25 25 25 10 10 10 10 5 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis (S1) tdis (S2) tdis (BC1) tdis (BC2) tdis (OE) ten(S1) ten(S2) ten(BC1) ten(BC2) ten(OE) tV(A)
(3) WRITE CYCLE
Limits Symbol Parameter Units Min 70 55 0 60 60 60 60 60 35 0 0 25 25 5 5 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW Write cy cle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect to W tsu(BC1) By te control 1 setup time tsu(BC2) By te control 2 setup time tsu(S1) Chip select 1 setup time tsu(S2) Chip select 2 setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recov ery time tdis (W) Output disable time f rom W low tdis (OE) Output disable time f rom OE high ten(W) Output enable time f rom W high ten(OE) Output enable time f rom OE low
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~17 ta(BC1) BC1,BC2
(Note3)
tCR
ta(A) or ta(BC2)
tv (A)
tdis (BC1) or tdis (BC1) ta(S1)
(Note3)
S1
(Note3)
tdis (S1) ta(S2)
(Note3)
S2
(Note3)
tdis (S2) ta (OE)
(Note3)
OE
(Note3) W = "H" lev el
ten (OE) ten (BC1) ten (BC2) ten (S1) ten (S2) tCW
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W control mode )
A0~17
tsu (BC1) or tsu(BC2) BC1,BC2
(Note3) (Note3)
S1
(Note3)
tsu (S1)
(Note3)
S2
(Note3)
tsu (S2)
(Note3)
OE tsu (A) W tdis(OE) DQ1~16
tsu (A-WH) tw (W) tdis (W)
trec (W) ten(OE) ten (W)
DATA IN STABLE
tsu (D)
th (D)
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
A0~17 tsu (A) BC1,BC2 S1
(Note3)
tCW
tsu (BC1) or tsu (BC2)
trec (W)
(Note3)
S2
(Note3) (Note5) (Note4) (Note3) (Note3)
W
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1 control mode)
A0~17
tCW
BC1,BC2
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Write cycle (S2 control mode)
A0~17
tCW
BC1,BC2
(Note3)
tsu (A)
tsu (S2)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Vcc Parameter Limits Test conditions Min Ty p Max Units V V V
(PD) Power down supply voltage Byte control input BC1 & BC2
VI (BC) VI (S1) VI (S2)
Chip select input S1 Chip select input S2
Vcc=3.0V 1) BC1 and BC2 > Vcc-0.2V = S1 <0.2V or S2 > Vcc-0.2V = = other inputs=0~3V 2) S1 >Vcc - 0.2V = other inputs=0~3V 3) S2 0.2V other inputs=0~3V
2.0 2.0 2.0 0.2
+85C +70C +40C 0 ~ +25C -20 ~ +25C -40 ~ +25C
V
-
1 0.3 0.3 0.3
30 15 3 1 1 1
A A A A A A
Icc
(PD)
Power down supply c urrent
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recov ery t ime Test conditions Min
Typical value is for Ta=25C
Limits Ty p Max
Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC control mode Vcc tsu (PD) BC1 BC2 S1 control mode Vcc 2.2V BC1 , BC2 > Vcc - 0.2V =
Note 7: On the S1 mode , the lev el of S2 must be f ixed at S2 > Vcc - 0.2V or S2 = 0.2V.
2.7V
2.7V
trec (PD) 2.2V
tsu (PD) 2.2V S1 S2 control mode Vcc S2 0.2V tsu (PD)
2.7V
2.7V
trec (PD) 2.2V
S1 > Vcc - 0.2V =
2.7V S2 0.2V
2.7V
trec (PD) 0.2V
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M5M5V416BUG - 70H I
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Revision History Revision No. 01
History The first edition
Date 17th July '00
Remark
MITSUBISHI ELECTRIC
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Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
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